The present invention is related to static control speculation of load instructions supported by modem processor architectures, such as the Intel® IA-64 processor architecture. Control speculation of load instructions allows a load instruction to be relocated, for optimization purposes, above a flow control point, conditional branch instruction, or predicate computation that, in corresponding, original, non-optimized code, controls whether or not the load instruction is executed. A check instruction is placed in the same position, relative to the conditional branch instruction, that is occupied by the load instruction in the non-optimized code. The processor defers certain exceptions that arise during execution of the relocated, control-speculative load instruction until a check instruction or other non-speculative instruction consumes the results of the load instruction. Currently, exception deferral strategies for control speculation of load instructions are statically determined, by compilers and operating systems, without the benefit of run-time information that might more accurately suggest whether or not certain types of exceptions arising during execution of load instructions should or should not be deferred. Designers and manufacturers of modem processors, as well as compiler developers and users of computer systems based on modern processors, have recognized the need for a method and system that allows for run-time determination of which exceptions and other long-latency operations that arise during execution of speculative loads should be deferred.